1. Field of Invention
The present invention relates to a semiconductor device structure and its method of manufacture. More particularly, the present invention relates to a polysilicon metal gate structure and its method of manufacture.
2. Description of Related Art
As the level of integration of semiconductor devices continues to increase, dynamic random access memory (DRAM) having gigabyte storage capacity is routinely manufactured. To reduce resistance-capacitance (RC) delay in a device gate, a polysilicon metal gate having a stacked structure has been employed. A polysilicon metal gate has a structural design that includes a refractory metal layer, a barrier metal layer and a polysilicon layer. For example, compared with a refractory metal layer made of tungsten, a polysilicon metal gate made of tungsten silicide (WSix) is much better at reducing the sheet resistance of the polysilicon metal gate. Furthermore, the gate is fabricated through a dry etching operation in a reactive ion etching (RIE) operation. Since a polysilicon metal gate has a smaller aspect ratio than a polycide metal gate, fabrication of self-aligned contacts is easier.
In general, a re-oxidation process is conducted after the gate is formed so that reliability of the gate oxide layer within the gate is improved and any damages to its internal structure during dry etching are repaired. However, the refractory metal layer (tungsten) is easily oxidized into tungsten oxide at the temperature level required for the re-oxidation process. Tungsten oxide is an insulating material so that resistance of the gate will increase and ultimately affect gate performance. To reduce tungsten oxidation, a selective oxidation process is used. Selective oxidation permits oxidation of exposed silicon surfaces without oxidizing the metal in an exposed metallic layer. Nevertheless, selective oxidation requires a high reactive temperature and hence results in a high thermal budget. Attempts to reduce thermal budget include forming a cap layer such as a silicon nitride layer over the gate structure prior to re-oxidation. The cap layer encloses the gate structure such that only the gate oxide layer is exposed. However, forming a silicon nitride layer over the gate structure means that the polysilicon layer is entirely enclosed by the silicon nitride and re-oxidation reaction at the gate corners is particularly difficult.
An alternative method for resolving the problems due to re-oxidation is to enclose the gate structure with a cap layer but expose the polysilicon layer on each side of the gate. This facilitates the re-oxidation at the corners of the gate. Yet exposing the polysilicon layer on each side of the gate structure and carrying out a re-oxidation process may produce a thick silicon oxide layer attached to the polysilicon sidewall. In the memory cell array of a dynamic random access memory (DRAM), an increase in thickness at the gate sidewall will reduce the outer diameter of subsequently formed contact openings. Such reduction in diameter renders the deposition of conductive material into contact openings increasingly difficult.